ASIC IP Cores for GPUs
Digital ASIC design on PowerVR mobile GPU IP — licensed to Apple, Intel, Samsung, Texas Instruments, MediaTek and others, and shipped in billions of devices.
A few of the shipping SoCs built around PowerVR graphics IP.
Product
PowerVR is licensable GPU IP, not a finished chip — a configurable, heavily verified core that customers integrate into their own SoCs. Bar is high: correct first time, portable across nodes and configs, competitive on performance per milliwatt.
Architecture is tile-based and deferred: tiles processed in parallel in on-chip memory, visibility resolved before shading so only visible pixels burn power. My work centred on the unified shading cluster (USC) — the heart of PowerVR GPUs: the multi-threaded core that runs vertex, pixel and compute concurrently across parallel scalar ALU pipelines — plus the logic that keeps them fed: local memories, DMA, address generation, hazard detection, priority queues and pipeline control.
Typical cycle: new graphics/compute API revision → hardware implications → top-level spec → block split across the team → implement, review, verify, synthesise and power-analyse. Mentored engineers, ran reviews and interviews as the group scaled; helped raise methodology (lint, formal, coverage, stronger test strategy).
Key Features
- Digital ASIC / RTL design · micro-architecture · licensable IP delivery
- PowerVR GPUs in flagship phones, tablets, smart watches and SoCs worldwide
- Tile-based deferred rendering — power and bandwidth efficiency for mobile
- Unified Shading Cluster (USC): heart of the GPU — multi-threaded pipelines (vertex / pixel / compute)
- Scalar SIMD datapaths · mixed FP32 / FP16 precision for area and power
- Local memories, DMA, address generation/validation, hazards, priority queues, pipeline control
- APIs to hardware: OpenGL / OpenGL ES, DirectX, OpenCL — spec through ISA impact
- Verification: directed and random tests, lint, formal, code and functional coverage
- Sign-off: synthesis, timing, power analysis, gate-level simulation
- Technical leadership: specs, design reviews, mentoring, recruitment